The semiconductor industry is developing so rapidly that related technologies and materials are evolving to improve ceaselessly the integration densities of integrated circuit devices and the performances thereof. As for the specific requirements of extremely fine devices and highly dense chips for sub-micron processes, the accuracy of pattern definition must be strictly observed, as well as the characteristics and qualities of areas in devices. For example, the intervals between each functional area of metal oxide semiconductor field effect transistors (MOSFETs), such as sources, drains, or gates, are closer due to the downsized MOSFETs. As a result, the sheet resistances of source/drain areas are increased. Therefore a self-aligned silicidation (SALICIDE) technology is adopted to lower the resistances of source/drain areas, and is applied widely in semiconductor processes.
The self-aligned silicidation process usually accompanies a resist protective oxide (RPO) process, by which a resist protective oxide layer is deposited on some device area of a wafer for protecting the area underlying the resist protective oxide layer from silicidation. The resist protective oxide process is also called SALICIDE blocking process. For brief description herein, “resist protective oxide process” is drafted through the whole application. FIG. 1 illustrates a portion of a prior art device area after performing the resist protective oxide process. Referring to FIG. 1, a device area 112 is separated from other active areas by a shallow trench isolation (STI) structure 108. Before the self-aligned silicidation process is performed, a resist protective oxide layer 125 is formed on the device area 112 not to be silicided. The formation of the area of the resist protective oxide layer 125, however, is not easily controlled. For instance, an over-etching step is generally used to remove the resist protective oxide layer on the shallow trench isolation structure 108 completely. Unfortunately, the overetch step inevitably etches away part of the shallow trench isolation structure 108, causing corners of the shallow trench isolation structure 108 to be recessed. The recessed corners lead to junction leakage associated with silicides formation in the following self-aligned silicidation process. In addition, the over-etching step may also etch away the edge 136 of the resist protective oxide layer 125 on which silicides are formed in the following self-aligned silicidation process, resulting in the decreasing resistance of the device area 112. Even though expanding the formation area of the resist protective oxide layer 125 horizontally may protect the edge 136 from being recessed by over-etching. The processes are operated more difficultly due to the closer intervals between the device area 112 and other active areas, as advancing to downsize resultant devices. As a result, the expanded resist protective oxide layer 125 influences on the properties of other active areas. Moreover, if too little etching is performed, traces of the resist protective oxide may contaminate other regions of the device area 112, such as, for instance, a contact hole. The resultant devices are thus unstable, and may even suffer from short circuits.